The performance of an op-amp is characterized by a number of performance measures such as open-loop voltage gain, quiescent power, input-referred noise, output voltage swing, unity-gain bandwidth, input offset voltage, common-mode rejection ratio, slew rate, die area, etc. These performance measures are determined by the design parameters, e.g., transistor dimensions, bias currents, and other component values. Analog integrated circuits are still largely designed by engineers performing discrete computations, and then verifying circuit operation with simulation systems. By contrast digital integrated circuits are automatically synthesized from high level design specifications using computer-aided design (CAD) software tools.
Most digital integrated circuits are fabricated using complementary-metal-oxide-semiconductor (CMOS) processes. The numerous performance and cost advantages of combining related circuit blocks in a single integrated circuit device provide strong incentives to include required analog circuitry on the same die as the related digital circuitry. Designing analog circuits in a CMOS process further complicates the analog design process. As a result, the time required to design the analog portions of an integrated circuit generally is far greater than the time required to design the digital component of the circuit, even though the digital component typically constitutes the majority of the system.
A variety of limited CAD tools have been developed for analog circuit design, including optimization tools. General purpose conventional optimization methods, such as steepest descent, sequential quadratic programing and Lagrange multiplier methods, have been widely used in analog circuit CAD. For widely used general purpose optimization codes, see:
P. E. Gill, W. Murray, M. A. Saunders and M. H. Wrige, "User's guide for NPSOL (Version 4.0): A FORTRAN package for nonlinear programming," Tech. Rep. SOL 86-2, Operations Research Dept., Stanford University, Stanford, Calif. 94305, January 1986; and PA1 B. A. Murtagh and M. A. Saunders, "MINOS 5.4 user's guide," Tech. Rep. SOL 38-20R, Systems Optimization Laboratory, Stanford University, Stanford, Calif. 94305, December 1983. PA1 H. Onodera, H. Kanbara, and K. Tamaru, "Operational amplifier compilation with performance optimization," IEEE Journal of Solid-State Circuits, vol.25, pp. 4660473, April 1990; PA1 H. Y. Koh, C. H. Sequin, and P. R. Gray, "OPASYN: A compiler for CMOS operational amplifiers," IEEE Transactions on Computer-Aided Design, vol. 9, pp. 113-125, February 1990; PA1 G. Jusuf, P. R. Gray, and A. Sangiovanni-Vincentelli, "CADICS--cyclic analog-to-digital converter synthesis," in Proceedings IEEE Intemational Conference on Computer-Aided Design, 1990, pp. 286-289; PA1 R. Chadha, K. Singhal, J. Vlach, E. Christen, and M. Vlach, "WATOPT: An optimizer for circuit applications," IEEE Transactions on Computer-Aided Design, vol. 6, pp. 472-479, May 1987; and PA1 J. P. Harvey, M. I. Elmasry, and B. Leung, "STAIC: An interactive framework for synthesizing CMOS and BiCMOS analog circuits," IEEE Transactions on Computer-Aided Design, vol. 11, pp.1402-1417, November 1992. PA1 Z. Ning, T. Mouthaan, and H. Wallinga, "SEAS: A simulated evolution approach for analog circuit synthesis," in Proceedings IEEE Custom Integrated Circuits Conference, 1991, pp.5.2.1-5.2.4; and PA1 W. Kruiskamp and D. Leenaerts, "DARWIN: CMOS op amp synthesis by means of a genetic algorithm," in Proceeding of the 32.sup.nd Annual Design Automation Conference, 1995, pp. 433-438. PA1 A. Torralba and J. Chavez and L. G. Franquelo, "FASY: A fuzzy-logic based tool for analog syntheses," IEEE Transactions on Computer-Aided Design, vol.15, pp. 705-715, July 1996. PA1 M. G. R. Degrauwe, 0. Nys, E. Dijkstra, J. Rijmenants, S. Bitz, B. L. A. G. Goffart, E. A. Vittoz, S. Cxerveny, C. Meixenberger, G. Van Der Stappen, and H. J. Oguey, "IDAC: An interactive design tool for analog CMOS circuits," IEEE Journal of Solid-State Circuits, vol. 22, pp.1106-115, December 1987; PA1 R. Harjani, R. A. Rutenbar, and L. R. Carley, "OASYS: A framework for analog circuit synthesis," IEEE Transactions on Computer-Aided Design, vol. 8, pp.1247-1265, December 1989; PA1 F. El-Turky and E. E. Perry, "BLADES: An artificial intelligence approach to analog circuit design," IEEE Transactions on Computer-Aided Design, vol. 8, pp. 680-692, June 1989; and PA1 S. K. Gupta and M. M. Hasan, "KANSYS: A CAD tool for analog circuit synthesis," in Proceedings of the 9.sup.th International Conference on VLSI Design, 1996, pp. 333-334. PA1 D. F. Wong, H. W. Leong, and C. L. Liu, Simulated Annealing for VLSI design, Kluwer, 1988; PA1 P. J. M. van Laarhoven and E. H. L. Aarts, Simulated Annealing: Theory and Applications, D. Reidel, 1987; PA1 E. S. Ochotta, R. A. Rutenbar, and L. R. Carley, "Synthesis of high-performance analog circuits in ASTRX/OBLX," IEEE Transactions on Computer-Aided Design, vol.15, pp. 273-293, March 1996; PA1 G. G. E. Gielen, H. C. C. Walscharts, and W. M. C. Sansen, "Analog circuit design optimization based on symbolic simulation and simulated annealing," IEEE Journal of Solid-State Circuits, vol. 25, pp. 707-713, June 1990; and PA1 H. Z. Yang, C. Z. Fan, H. Wang, and R. S. Liu, "Simulated annealing algorithm with multi-molecule: an approach to analog syntheses," in Proceedings of the 1996 European Design & Test Conference, 1996, pp. 571-575. The main disadvantages of simulated annealing are that it can be very slow, and that it cannot in practice guarantee a globally optimal solution. PA1 h(.lambda.y+(1-.lambda.)z).ltoreq..lambda.h(y)+(1-.lambda.)h(z). PA1 minimize log .function..sub.0 (e.sup.y1, . . . , e.sup.yn) PA1 subject to log .function..sub.i (e.sup.y1, . . . , e.sup.yn).ltoreq.0, i=1, . . . , m
For other CAD methods based on conventional optimizations, see:
The primary problem with these conventional optimization tools is that they only find the locally optimal designs. This means that the design is at least as good as neighboring designs, i.e., small variations of any of the design parameters results in a worse (or infeasible) design. However, this does not mean that the design is the best that can be achieved, i.e., globally optimal. In fact, it is often the case that some other set of design parameters far away from the one produced by a local optimum, is better.
One approach to attempting to avoid this problem is to start the optimization method from many different initial designs, and to take the best result. However, it is still uncertain whether the result is the best possible design; this method merely increases the likelihood of finding the globally optimal design. Furthermore, this approach is often highly computational and time intensive. Furthermore, human intervention is required to evaluate the different optimization results and select one that is viewed to be the best. In addition these conventional optimization methods become even slower when used with complex device models.
Knowledge-based and expert-system methods have also been widely used in analog circuit CAD. Examples include generic analog or evolution systems, for instance see:
For systems based on fuzzy-logic, see:
For some heuristic-based systems, see:
These methods have several disadvantages. They find a locally optimal design (or, even just a "good" or "reasonable" design) instead of a globally optimal design. The final design depends on the initial design chosen and the algorithm parameters. As with classical optimization methods, infeasibility is not unambiguously detected; the method simply fails to find a feasible design (even when one may exist). Also, these methods require substantial human intervention either during the design process, or during the training process.
Optimization methods that determine globally optimal designs have also been developed for analog circuit design. Two widely known global optimization methods are branch and bound and simulated annealing. Branch and bound methods are iterative methods. In each iteration a suboptimal feasible design and also a lower bound on the achievable performance is maintained. This enables the algorithm to terminate with a global design within a given tolerance. A disadvantage of branch and bound methods is that they are extremely slow, and computation requirements grow exponentially with the size of the optimization problem. Even problems with ten variables can be extremely challenging.
Simulated annealing is another method which can in theory compute a globally optimal design, however, no real-time lower bound is available, so termination is heuristic. See for instance,
The thermal logic synthesizer (TILOS) optimization system applies geometric programming to digital circuit design, and more specifically to transistor and wire sizing for Elmore delay minimization, as described in U.S. Pat. No. 4,827,428. The geometric programs that arise in Elmore delay minimization are very specialized (the only exponents that arise are 0 and .+-.1). Furthermore, the representation of the problem as a geometric program is only approximate (since the actual circuits are nonlinear, and the threshold delay, not Elmore delay, is the true objective).
Thus an improved optimization system that quickly generates globally optimal designs for a wide range of performance specifications, and readily scales with many variable problems would be highly desirable.